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A6402
(R)
Universal Asynchronous Receiver/Transmitter
Data Sheet
September 1996, ver. 1
Features
s s s s s s s
A6402 MegaCore function implementing a universal asynchronous receiver/transmitter (UART) Optimized for FLEX(R) and MAX(R) architectures Uses approximately 162 FLEX logic elements (LEs) Programmable word length, stop bits, and parity Full duplex operation Includes status flags for parity, framing, and overrun errors Functionally based on the Harris HD-6402 device, except as noted in the "Variations & Clarifications" section on page 63
General Description
The A6402 MegaCore function implements a universal asynchronous receiver/transmitter (UART), which provides an interface between a microprocessor and a serial communications channel. See Figure 1.
Figure 1. A6402 Symbol
A6402
cls1 cls2 crl ndrr epe mr pi rrc rri sbs ntbrl tbr[7..0] trc
dr fe oe pe rbr[7..0] tbre tre tro
Altera Corporation
A-DS-A6402-01
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A6402 Universal Asynchronous Receiver/Transmitter Data Sheet
Ports
Table 1 shows the input and output ports for the A6402.
Table 1. A6402 Ports
Name
cls1 cls2
Type
Input
Polarity
-
Description
Character length select bits. These bits determine the length of the data word. 00 = 5-bit word format 01 = 6-bit word format 10 = 7-bit word format 11 = 8-bit word format Control register load. Controls how the data word is loaded into the control register. Data received reset. Clears the dr output. Even parity enable. When high, even parity; when low, odd parity. Master reset. Clears the pe, fe, dr, and oe outputs, and asserts the tre and tbre outputs. Parity inhibit. When pi is asserted, parity is neither generated nor checked. Receiver register clock. Operates at 16 times the receive data rate. Receiver register input. Serial input data. Stop bit select. When high, sbs generates 2 stop bits (1.5 stop bits for 5-bit format); when low, sbs generates 1 stop bit. Transmitter buffer register load. Enables load of the transmitter buffer register. Transmitter buffer register input bus. Transmitter register clock. Operates at 16 times the transmit data rate. Data received. Indicates that a data word has been transferred to the receiver buffer register. Framing error. Asserted when the expected stop bit(s) is not detected. Overrun error. Asserted when data in the receiver buffer register is overwritten while the dr output is still asserted. Parity error. Set when the calculated parity does not match the received parity. When pi is asserted, pe is set low. Receiver buffer register bus. Transmitter buffer register empty. Indicates that the transmitter buffer register is empty. Transmitter register empty. Indicates that the data word is completely transmitted out of the transmitter register. Transmitter register output. Serial output data.
crl ndrr epe mr pi rrc rri sbs ntbrl tbr[7..0] trc dr fe oe pe rbr[7..0] tbre tre tro
Input Input Input Input Input Input Input Input Input Input Input Output Output Output Output Output Output Output Output
High Low High/low High High - - High/low Low - - High High High High/low - High High -
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Altera Corporation
A6402 Universal Asynchronous Receiver/Transmitter Data Sheet
Configurations
The A6402 receives and transmits data in a variety of configurations, including 5-, 6-, 7-, or 8-bit data words; odd, even, or no parity; and 1, 1.5, or 2 stop bits. Table 2 shows the available configuration options.
Table 2. A6402 Available Configurations
Character Format Data Bits Parity Bit
5 Odd Odd Even Even None None 6 Odd Odd Even Even None None 7 Odd Odd Even Even None None 8 Odd Odd Even Even None None Note:
(1) The X indicates "don't care."
Control Word Stop Bits
1 1.5 1 1.5 1 1.5 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2
Start Bit
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
cls2
0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1
cls1
0 0 0 0 0 0 1 1 1 1 1 1 0 0 0 0 0 0 1 1 1 1 1 1
pi
0 0 0 0 1 1 0 0 0 0 1 1 0 0 0 0 1 1 0 0 0 0 1 1
epe Note (1)
0 0 1 1 X X 0 0 1 1 X X 0 0 1 1 X X 0 0 1 1 X X
sbs
0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
Altera Corporation
59
A6402 Universal Asynchronous Receiver/Transmitter Data Sheet
Functional Description
Figure 2. A6402 Block Diagram
crl cls2 cls1 pi epe sbs tbre tre
Figure 2 shows a block diagram of the A6402.
Control Register
Transmitter
Transmitter Control
mr ntbrl trc
Start Transmitter Buffer Register Transmitter Register Parity Generator Transmitter Multiplexer tro
tbr
8
Stop
dr oe mr ndrr rrc Receiver Control
Receiver
rri
rbr
8
Receiver Buffer Register
8
Receiver Register
8
pe
Parity Check Stop Check
fe
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Altera Corporation
A6402 Universal Asynchronous Receiver/Transmitter Data Sheet
Master Reset
When the mr input is asserted, the pe, fe, oe, and dr outputs are asynchronously cleared and tbre and tre are asserted. The assertion of mr also sets all state machines to a default idle state. This condition does not affect the receiver buffer register. The mr input must be pulsed high at least once after power-up. When mr is deasserted, normal operation resumes at the next rising edge of trc or rrc. 1 Once the pe, fe, and oe outputs are set, the only exit condition available is through asserting mr.
Control Register
The control register contains the configuration of the data word, including the number of bits, calculated parity, and the number of stop bits. The crl input, an active high register enable, controls how the data word is loaded into the control register. When crl is asserted, the cls2, cls1, pi, epe, and sbs inputs are loaded on the next rising edge of the trc input.
Transmitter
The transmitter consists of the following elements:
s
Transmitter control--The transmitter control contains three interconnected state machines. The first state machine regulates the baud rate by performing a divide-by-16 operation on the trc input. The second state machine detects the low-to-high transition on ntbrl, starts the serial transmission through tro, transfers data from the transmitter buffer register to the transmitter register, and generates the status signals tbre and tre. The third state machine controls the multiplexing of data bits to the tro output. Transmitter buffer register--The transmitter buffer register is loaded via ntbrl, an active-low register enable, that causes tbr[7..0] to be loaded from the microprocessor on the next trc clock edge. Transmitter register--The transmitter register loads the data from the transmitter buffer register and holds that data until transmission is complete.
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Altera Corporation
61
A6402 Universal Asynchronous Receiver/Transmitter Data Sheet s
Parity generator--The parity generator calculates the appropriate parity value depending on the epe input (even or odd parity) and the cls inputs (data word length). Transmitter multiplexer--The transmitter multiplexer selects a single-bit data value and drives the tro output. Inputs to the transmitter multiplexer include the start bit, all eight bits from the transmitter register, the parity bit, and a stop or idle bit.
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Receiver
The receiver consists of the following elements:
s
Receiver control--The receiver control contains three interconnected state machines. The first state machine performs a divide-by-16 operation on the rrc clock to determine when to sample the rri serial input. The second state machine detects the high-to-low transition on rri, determines if a valid start bit has been received, transfers data from the receiver register to the receiver buffer register, and generates the status signals dr and oe. The third state machine loads the individual bits of the receiver register and the fe and pe outputs. Receiver register--The receiver register loads the number of data bits determined by the cls inputs. If the data word is less than eight bits, the data is right-justified with the MSBs filled with logic lows. When the stop bit is detected, the receiver register transfers its contents to the receiver buffer register. Parity check--The parity check calculates the parity of the data word and the parity bit. If an error occurs, the pe output is asserted. Once asserted, the pe output can only be cleared by asserting the mr input. Stop check--The stop check samples the middle of the first expected stop bit. If an error occurs, the fe output is asserted. Once asserted, the fe output can only be cleared by asserting the mr input.
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Altera Corporation
A6402 Universal Asynchronous Receiver/Transmitter Data Sheet
Timing Waveforms
Figure 3 shows the timing waveforms for the A6402.
Figure 3. A6402 Functional Timing Waveforms
Data Input Cycle
trc tbr[7..0] ntbrl Valid Data
Control Register Input Cycle
trc cls[2..1], pi epe, sbs crl Valid Data
Serial Data Format (7 Bits, 1 Parity Bit, 1 Stop Bit)
Start Data LSB
tro
Data Parity Stop MSB
Variations & Clarifications
The following characteristics distinguish the Altera(R) A6402 from the Harris HD-6402:
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The A6402 does not contain the sfd and rrd inputs, and the outputs are not tri-stated. In the A6402, the control and transmitter buffer registers are implemented as registers and use trc as a clock source; these registers are implemented as latches in the HD-6402 device. In the A6402, after mr is deasserted, normal operation can resume on the next rrc or trc rising clock edge. In the HD-6402 device, normal operation does not resume for 18 clock cycles. Due to the synchronization process in the A6402, tbre is deasserted two clock cycles after the low-to-high transition of ntbrl. In the HD-6402 device, tbre is deasserted immediately after the low-to-high transition of ntbrl. In the A6402, the tro output is registered to remove glitches. This register uses trc as the clock source. Once the pe, fe, and oe outputs are asserted, the HD-6402 device has no exit condition other than through asserting mr.
Altera Corporation
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Copyright (c) 1995, 1996, 1997, 1998, 1999 Altera Corporation, 101 Innovation Drive, San Jose, CA 95134, USA, all rights reserved. By accessing this information, you agree to be bound by the terms of Altera's Legal Notice.

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